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ASAHI KASEI
[AK2358FI
Base-band 1S1 for kopian Cordless Telephones(CTl, CT1+)
I
*1 *1
Features Meets to the specification of the europian cordless telephones (CT1, CT1+) Built-in voice filter for cordless telephone, MSK MODEM (2400bps), COMPANDOR, and scrambler circuit *1 Low / wide operation voltage range (1.9 V to 5.5V) *1 Built-in COMPANDOR output transient response circuit and time constant circuit *1 No external component is needed for COMPANDOR *1 Built-in buffer amplifier for ceramic receiver driving. *1 Built-in electronic volume for microphone sensitivity and modulator/demodulator sensitivity *1 Receiving level switchable in 8 steps (-12 to +9dB) *1 Built-in u uting function for voice transmitting and receiving *1 External adjustment for the limiter level *1 Built-in amplifier for transmission and reception gain adjustment *1 Low power CMOS and power-down function u Built-in 3.58MHz oscillator circuit *1 Scrambler circuit with frequency inversion. Two inversion frequencies can be selected. *1 Bypassing the scrambler circuit available u Built-in frame detection function for the MSK demodulator u Control register and MSK MODEM data buffer controlled by serial interface *1 Few external component is necessary resulting cost reduction and small set size. El Package: 24 pin VSOP Block Diagram
I
I
splatter f i lter Transmission s i g n a l output
IT D a t a / R x D a t a Control data (
3 .58NHz \ control register i and data buffer !4S1 MODEM
!rane d e t e c t i o n Reception signal Receiver input
Eecept inn nutput
0152 E 00
1996/12
o u-l (w PY o
.
.
TXINO
a TXIN
3:
.......................
TXHPF +VR1 Compressor A ?!
r
TXAFSW J Scrambler Preemphasis~ TAGND Limiter 4 A Splatter filter 6
0
+VR2
TDATA TCLK OIR SCLK 01/0 ROF/FD
9 ~a 13 12
4
>
10 ~11
> >
Control register and data buffer
..................
~
_
MSK Modulator
TC
Y USK Denodulator
EN
Y
a
..... . `~ . . . . . , .,:
BUFON
.................
..............
PCONT Deemphasis +I J&&J 4 Expander A `$ De~ Scrambler v RXHPF +VR3 j ................... RXIN m 22 ...............
T
RXAFSW RECSW , . . . . . . . . . . . . . . . . . *~- +kMP3,.,;: 4+
I
v
R e eiver
1
1
BUFOP
19
Y
18
Y71'I
17
Y
16
v
7
"
Operating mode
w
ASAHI KASEI
[
[AK2358FI Description
I
The AK2358F, abase-band LSI for europian cordless telephone (CT1, CT1+), has built-in voice filters, a 2400bps MSK MODEM for data communication, a frame detection circuit, a COMPANDOR for noise reduction, and scrambler circuits. The CMOS process provides low power operation. Application of 24 pin VSOP package with the feature of significant reduction of external component provides minimum mounting area. The time constant circuit for the COMPANDOR output transient response is built into the LSI. Using a 2400bps MSK MODEM for data communication has realized high data reliability and high speed communication at the same time. This LSI is suitable for cordless system telephones etc. which requires complicated protocol control. An oscillation circuit with a 3.58MHz crystal oscillator is built in, and no other frequency source is required for the MSK MODEM. The oscillator also can be used for the other DTMF generator etc. The scrambler circuit uses the simple inversion u ethod with inversion of the voice spectrum around the carrier frequency. Two inversion frequencies can be selected. Built-in electronic volumes provided for transmission and reception part realize automatic adjustment of the microphone sensitivity and the modulator/demodulator sensitivity by external EEPROM and microprocessor. The transmission part is composed of high-pass filter, compressor, pre-emphasis circuit. scrambler, limiter, MSK modulator, splatter filter, electronic volume control, etc. The reception part is composed of band pass filter, de-emphasis circuit, de-scrambler, expander, buffer amplifier, MSK demodulator, frame detection circuit, electronic volume control, etc.
s Pin Arrangement
24pin VSOP
AGNDINC 1 0 TAGNDC 2 TXINC 3 TXINOC 4 LIMLVC 5 MODC 6 Vssc 7 TCLKC 8 TDATAC 9 D1/Oc 10 ROF/FDc 11 SCLK ~ 12
24 a RAGND 23 -J XXIN 22 -J RXINO 21 -J BUFOP 20 -J BUFON 19 -J RXAF 18 aBxAFIx 17 3 EXPOL'T 16 3 VDD 15 3 X1X 14 3 XOL'I 13 ~DIR
0152-E-00 -3-
199612
ASAHI KASEI
[AK2358FI Circuit Configuration
I
Block AMP1
I
TXHPF Compressor Pre-emphasis
Scrambler (Tx)
Limiter
Splatter filter
MSK modulator AMP2
RXLPF
RXHPF De-emphasis De-scrambler (Rx)
Function The operational amplifier for voice signal transmission gain adjustment and for the filter to eliminate aliasing noise by the SCF(switched capacitor filter) in the following stage. Use an external resistor and capacitor to set the gain less than 30dB and the cut-off frequency to about 10kHz. The SCF circuit to eliminate the low frequency component less than 300Hz from the transmission voice signal. The circuit to compress the amplitude of the transmission voice signal. The circuit to emphasis the high-frequency component of the transmission voice signal to improve the S/N of the modulation signal. The circuit to inverse the transmission voice spectrum in regard to the carrier frequency. Carrier frequency can be selected from two frequencies by KEY. PCONT select to use the scrambler or the pre-emphasis circuit. The amplitude-limiting circuit to suppress the frequency deviation of the modulation signal. The limitation level can be adjusted by applying a DC voltage to the LIMLV pin. If the LIMLV pin is open, the default limitation level is applied. The SCF circuit to eliminate the high frequency component higher than 3.4kHz from the limiter output signal or the MSK u odulator signal. The circuit to generate a 2400bps MSK signal according to the received digital signal logic from the TDATA pin. The operational amplifier to adjust the reception demodulation signal gain and for the filter to eliminate the aliasing noise of the SCF in the following stage. Set the gain to less than 30dB and the cut-off frequency to about 10kHz by external resister and capacitor. The SCF circuit to eliminate the high frequency component higher than 3.4kHz from the limiter output signal or the MSK modulator signal. The SCF circuit to eliminate the low frequency component lower than 300Hz from the reception voice signal. The circuit to de-emphasis the emphasized signal by pre-emphasis circuit. The circuit to re-inverse the spectrum of the scrambled receiving voice signal respect to the carrier frequency. Carrier frequency can be selected from two candidates by a KEY. The de-scrambler(Rx) or ~he reemphasis circuit can be selected by PCONT. `the circuit to expand the signal amplitude compressed by the compressor.
Expander
0152-E-00 "4-
1996, 12
ASAHI KASEI Block AMP3
[AK2358FI Function The operational amplifier used on the smoothing filter of the reception SCF output. Set the gain to OdB and the cut-off frequency to about 20kHz by external resister and capacitor. The SCF circuit to eliminate the low frequency component lower than 100Hz from the reception MSK signal. The circuit to reproduce the 2400bps receiving data and the clock from the received MSK signal in the RXIN pin. The inverting and the non-inverting buffer amplifier to drive the ceramic receiver. The circuit to generate the reference voltage for the internal analog signal. The circuit to oscillate the 3.58 MHz reference clock using an external crystal oscillator and resistor. The volume to control the input amplitude of the transmission voice signal. The adjustment range is -8dB to +7dB by ldB step. The volume to control the MOD output amplitude. The adjustment range is -4dB to +3.5dB by 0.5dB step. The volume to control the input amplitude of the reception demodulation signal. "The adjustment range is -4dB to t3.5dB by 0.5dB step. The volume to control the receiving voice amplitude. The adjustment range is -12dB to +9dB by 3dB step. The control register contlols the status of internal switches and internal volumes of the LSI by serial data consists of 2 address bits and 8 data bits. At the start up a power-on-reset circuit works and the default values are set to the control register. (see control register map.) The data buffer stores 8 bits of the MSK receiving data to smooth the signal interface with CPU. Pin/Function I
MSKHPF MSK demodulator AMP4 A!!P5 AGND Oscillation circuit VR1 VR2 VR3
VR4 Control register and data buffer
I
Pin No. 1 Pin name AGNDIN
1/0 I
2
TAGND
o
3
TXIN
1
4 5
TXINO LIMLV
o 1
I
\
Function Analog ground input pin. Connect the capacitor to stabilize the analog ground. Analog ground pin for the transmission system. Connect the capacitor to stabilize the analog ground. Transmission voice input pin. This is the inverting input pin for AMP1. It composes a microphone amplifier with a external resister and a caDacitor. AilPl output pin. Limitation level adjustment pin. I The limitation level can be adjusted by applying a \ DC voltage to this pin. The default limitation level is adopted if no voltage is applied.
0152-E-00 5-
199612
ASAHI KASEI Pin No. 6 7 8 Pin name MOD Ws TCLK 1/0 o -- o
[AK2358FI Function Output pin of the modulated transmission signal. A load impedance larger than 10kQ can be driven. Negative power supply pin. Clock output pin for the MSK data transmission. A 2.4kHz clock is put out by setting the internal register TDE to "O". If the register is set to "1", it goes "H" level. MSK transmission data input pin. Data are latched synchronizing with the TCLK rising edge. Serial data input and output pin. MSK signal reception flag output and Frame detection signal output pin. This pin puts out two types of information, depending on the status of the internal register FSL. If FSL is "l", it is klSK signal reception mode, so the pin reaches low after 8 bits of the MSK reception signal have been written to the data register. If FSL is "O", it is the frame detection signal output mode, so the low pulse is put out after a frame pattern is detected. Clock input pin for serial data 1/0. Serial data 1/0 control pin. Crystal oscillator connection pin. The reference clock IC is generated by connecting a 3.58MHz crystal oscillator parallel to a lMf2 resistor between this pin and XIN pin. In case of external clock operation, connect XOUT pin to VSS and apply the clock to XIN. Crystal oscillator connection pin. Positive power supply pin. Expander output pin. Reception voice input pin. This is the inverting input of AMP3. It composes a smoothing filter by external resistor and capacitor. Reception voice output pin. This is the output pin of AVP3. A load impedance more than 10kQ can be driven. Receiver amplifier output pins. Connect the ceramic receiver between these two pins. AMP2 output pin. Demodulated receiving signal input pin. This is the inverting input of AUP2. [t composes a prefilter with external resistor and capacitor. Analog ground pin for the reception systcm. Connect the capacitor (o stabilize analog ground.
9
TDATA
I
10 11
DI/O RFD/FD
1/0 o
12 13 14
SCLK DIR XOUT
I I I
`1 5 16 17 18
XIN VDD EXPOUT RXAFIN
o -- o I
19
RXAF
o
20 21 22 23
BUFON BUFOP RXINO RXIN
o o o I
24
RiGiYD
o
0152-E-00 6-
199612
ASAHI KASEI
[AK2358FI Absolute Maximum Ratings I max 6.5
flo
I
VSS=OV; Note 1)
Parameter Power supply voltage: (VDD) Input current (except the power supply pins) Analog input voltage Digital input voltage Storage temperature
Symbol VA+
IIN
min -0.3
Unit v mA v v "c
VINA VIND
Ts tg
-0.3 -0.3 -55
(VA+)+O.3 (VA+)+O.3 130
Note l): All voltages with respect to the VSS pin. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Recommended VSS=OV; Note 1) Parameter 10~eration temperature Power supply ;oltage: (VDD) Analog reference voltage Current consumption Mode O Mode 1 hlode 2 Mode 3
I
Operating
Conditions
I Symbol I I, Ta VD+ AGND IddO lddl Idd2 Idd3
min I -lo 1:9
I I
tYD 2.0 l/2VD+ 0.1 0.9 1.4 5.5
I I
max 70 5:5 0.8 1.9 2.9 10
I Unit
I "c v v mA
Note 1): All voltages with respect to the VSS pin.
0152-E-00 -7
1996 12
ASAHI KASEI
[AK2358FI Analog Characteristic s 1
I
f=lkHz, PCONT=''1", TC="l", EM=''1", VR1 to VR4=OdB: unless otherwise specified, OdBm=O.775Vrms OdBx=-5dBm at AVDD=2V Note 8) 1) TX system Parameter Standard input level @TXINO Absolute gain TXINO--+MOD Note 1) MOD lkHz Limiter level Note 1) No external R Adjustment range by external R Compressor linearity TXINO~MOD Note 1) 2) TXINO=-44dBx TXINO=-50dBx Noise without input TXINO+MOD Note 1) 3) Compressor distortion TXINO-hlOD TXINO=-10dBx Transmission MSK Note 1) @MOD signal level 1.2kHz signal output Transmission MSK Note 1) @MOD signal distortion 1.2kHz si~nal outDut 2) RX system Parameter max Standard input level @RXINO Absolute gain RXINO~BUFON, BUFOP 0 -1.5 Note 1) RXINO-BUFON, BUFOP Expander linearity Note 1) 4) RXINO=-25dBx -33.0 -30.0 t -27.0 RXINO=-30dBx -45.0 -40.0 -35.0 Noise with no input RXINO-BUFON, BUFOP -70 Xote 1) 3) Expander distortion RXINO~RXAF RXINO=-5dBx Reception MSK @RXINO signal level 1.2kHz signal output Unit I dBx min 2.0 -4.5 typ -lo 3.5 -3.5 max 5.0 -2.5 -2.5 Unit dBx dB dBx
-
-20 -24
-17.0 -20.0
-14 -16 -36.5 -35
dB dBm dB dBx dB
-4.5
-3.5
-2.5 -32
T
-L
dB I dBm
T
0152-E-00
1996 12
8
ASAHI KASEI 3 ) Overall characteristics Parameter Absolute gain TXIliO~BUFO!l, BUFOP Note 5) TXINO=-10dBx KEY="O" or "l" TXINO~BUFON,BUFOP Note 3) 5) Distortion TXINO=-10dBx KEY="O" o r " l " Crosstalk Note 1) @BUFON,BUFOP Transmission ~ Reception -f~=fto. TXINO=OdBx Crosstalk Note 1) @MOD Reception * Transmission 6) 6) 7) -60 7) -56.5 min -0.5 typ 0 -50 max +2. 5 -43
[AK2358FI
Unit dB dB
dBx
dBx
4) Filter characteristics Parameter Transmission overall characteristics (See Fig.1) TXINO ~ MOD 100Hz TC="O" EM="l PCONT="l" 300Hz Relative value with OdB gain 3kHz a t lkHz 3. 4kHz 6kHz Reception overall characteristics (See Fig.2) RXINO ~ EXPOUT 100Hz TC="O" EM="l PCONT="l 250Hz Relative value with OdB gain 300Hz at lkHz 3. 4kHz 5kHz min typ m ax Unit
-12 8 8
-10.5 9.5 9.5
-40 -9
11 11 -12 -4 13.5 dB -9 -15 dB
9 -12
12 10.5 -10.5
Note 1) With the external circuit shown in the application circuit example. Note 2) Relative value with OdB as the MOD output level at the time of input of standard input level (-10dBx) to TXINO. Note 3) With the C-message filter. Note 4) Relative value with OdB as the BUFON, BUFOP output level at the time of input of standard input level (-10dBx) to RXINO. Note 5) With the external circuit shown in the application circuit example. Further, the AMP2 gain should be -3.5dB, and hfOD and RXIN should be in loop connection. Note 6) TC='' 1", PCONT="O" Note 7) TC=''O", PCONT="O" Note 8) The dBx is standardized unit valid for various power supply voltages from 1.9 to 5.5V. If the voltage is 2Y, OdBx should be -5dBm. With the other voltage as X [V], -5 } 20 log (X 2) dBml. OdBx
0152-E-00 -9-
1996/12
ASAHI KASEI *l Filter characteristics
GA IN(dB)
[AK2358FI
10' Fig. 1
,~2
,03
,04
FREQUENCY
Transmission overall characteristics
GAIN(dB)
10 0 -lo -20 -30 -40 -50 1I
/
I
,02 Fig. 2
,~3
FREQUENCY
I
,04
Rc'ceptiorl overall characteristics
0152 E-00
10
-
1996/'l2
ASAHI KASEI I 1) TX system Level Diagram
[AK2358FI I
UK MOdu I ator
f=lkHz TXINO
~
Uoo
dB) 10 0 -lo -al -30 -40 -50 -60 -70 -w
........ ........... ....... .......
"--- . . . . . . . . . . . . . . - 3 . SdBx(USK s i g n a l l e v e l ) -6.3dBx(reference l e v e l )
.
.
.
.
.......... .
-Z3.WBX -26.5,8X
....................... I
. . . . . . t. . . . . . . . . . . . . .
......... .......... .................... ....................... ..................... .......................
-90
2) RX system
f-1 kHz DEM RXINO EXPOUT RX*F BUFOP
a~~'HO';dBHp''';terH'''")=
-5,0 dBx 10
0
.........
. .
I -I
/
10 -lo . . ...--"..... "-.. `- . . . . . . . . .. .. .
22
$dBx(max.
output level)
-10 -al -25
.~
/
-4dBx(referenca I eve I )
""
-2
20
[..
F Ni I
.34,Bx ~~~~~~ / ; ~"
-40 -45 -50
-44dBx
I I
vote)
The dBx is standardized unit valid for var Ous pOwer supply vOltages frOm 1 . 9 tO 5.5V. [f the voltage is 2V, O d B x should be 5dBm. With the other ioltage as X [v:, OdBx = 5 I 20 log (X 2) dllm:.
11
ASAHI KASEI
[AK2358FI
Digital Characteristic s I Unit v I 30%VD+ I V I v \ 20%VD+I v 10 ] UA I I iuAl `v
0.3
I
1 . DC Characteristics
Parameter High-1evel inuut voltage 1 l Low-level inDut voltaze 1 High-level input voltage 2 Low-level input voltage 2 High-level inuut current l L o w - l e v e l inDut current -. ------ --igh-level output voltage Low-1evel outuut voltage (l). TDATA, DI/O (2) SCLK, DIR (3) TCLK, RDF, DI/O
min Pin Symbol 70%VD+ I (1) VIH1 I (1) I v,,., I I / 80%VD+ I VIH2 (2) VIL2 (2) V,H=VD+ (l)(2) IIH V,,=OV I (1)(2) I Ir, I `1O I 90%VD+ I~H=O. lmA (3) VOH `"1~~=0.6mA (3) VOL
"H-
typ
m ax
v
2. AC Characteristics Parameter Master clock frequency MSK Modulator timing TDE Falling to TCLK Rising TCLK period TDE Rising to TXAFSW Falling TDATA Set up time TDATA Hold time TDATA Hold time2 MSK Demodulator timing RCLK Period & FD pules width Serial data input timing Clock pulse width 1 Clock pulse width 2 SDATA Set Up time SDATA Hold time DIR Set up time DIR Hold time DIR falling to SCLK falling time SCLKi'DIR input rising time SCLK/DIR input falling time RDF falling to SCLK falling time SCLK rising to RDF falling time Symbol fclk T1 T2 T3 TS TH TH2 T ta tb tc td te tf tg th ti tj tk min typ 3.579545 208.3 416.7 2 1 1 2 402.2 416.7 max Unit MHz ,uS /!.Ls ms ps ps ,uS /ls ns ns ns ns ns ns ns ,uS ,uS ns ns
500 500 100
100 100 100 100 1 1
100
600
0152-E 00
- 12
1996/'12
ASAHI KASEI
[AK2358FI
TCLK TXAFSW N o t e ) ( Internal register ) TDE Note) ( Internal register ) TDATA MOD Voice signal Voice signal [ I
::
:
4
ta
; tb : \./ Y
SCLK DI/O DIR
~. . . . . . . . . . . . . . ..~ ..
..................
D7
D1
do
)
++
{-------- 0.8DVDD
SCLKIDIR input e) The timing to rewrite the internal registers TXAFSW and TDE is synchronized with the falling edge of DIR.
13
[AK2358FI
\ ....
1 1 1 1 1. . . . . .
+
w
*
k *
n
... ,..
/
""
/
,`
/
/'
.
~
2
:
z x w
x
CK
A: v:
1 ;
" 14
ASAHI KASEI
[AK2358FI
Control Register Map I
I
s Register composition
Address A l AO Control register 1 Volume register Volume register Control register 2 + volume register I Reception data register 0 o 1 1 0 1 0 1
D7 FSL 1 TC
D6 0S2 1
D5 BS1 1
Data D4 D3 FCLN 1 KEY PCONT RECSW
VR2 EM FRPT
D1 DO TXAF RXAF TDE `SW -Sw VR4 VR1 D2 VR3
MSK MODEhl reception data
The reception data register is a read only register. and the others are write only registers. The reception data register has no address information proceeding to the Data. Set the all bits D4 to D7 of volume register address "01" to "l". If they are set to "O", it changed to test mode.
s Register
u ap
1) Control register 1 Address A l AO o 0 (Default) Data D? FSL 1 D6 BS2 1 D5 BS 1 0 D4 FCLN 0 D3 PCONT 1 D2 TDE 1 D1 TXAFSW 0 DO RXAFSW 0
a) Transmission signal control TDE 1 1
I
TXAFSW 0 1
I
1
o
II
Transmission output Voice signal h[ute MSK simal
I
b) Reception signal control I
I
RXAFSW 1
RECSW
I II
o
o
1 0
RXAF hlute 0s 0s
[ BUFOP/BUFON I Nute I I Mute ON
c ) Scrambler circuit OY OFF [ PCONT 1 o !I I I 1 Bypass (Scrambler OFF) Scrambler works (ON)
0152-E-00
-15-
1996 12
ASAHI KASEI d) Frame detection circuit ON/OFF
1
[AK2358FI
o
The frame detection function is not used (OFF). The frame detection function is used (ON).
Note) FCLN automatically changes from O to 1 when a synchronized frame is detected. e) Power-down mode
BS2
1
BS 1
1
hlode name modeO model mode2 mode3
o
1 o
1 0
0
Voice system t transmission MSK OFF OFF OFF ON
Reception MSK OFF OFF ON ON
Oscillator OFF ON ON ON
) RDF/FD selection FSL 1 The MSK signal reception flag (RDF) is put out from the RDF/FD pin. The frame detection signal (FD) is ~ut out from the RDF/FD pin.
o
2) Control register 2 Address Al AO 1 1 , (Default) Data name KEY FRPT EM TC Data D7 TC 1 D6 EM 1 D5 FRPT
0
D4 KEY 1
D3 1
\
D2
0
I D1 \ VR3
0
DO
0
I
Function Carrier inverting frequency " 1 ": 3.496kHz "O": 3.729kHz Frame detector detection pattern "l": 1100010011010110 (base unit) "o" : 1001001100110110 (portable unit) Emphasis circuit " 1 ": Passage (ON) "O": Bypass (OFF) " 1 ": Passage (ON) COMPANDOR circuit "O": BvDass (OFF)
I
3) Volume register Address A l AO o 1 1 0 1 1 Data D7 1 VR23 TC D6 1 YR22 EM D3 1 YR21 f'RPT D4 1 VR20 KEY D3 RECSW VR13 VR33 D2 VR42 VR12 VR32 D1 VR4 I \'Rl I VR31 DO VR40 VR1O VR30
-16-
ASAHI KASEI a) VR1 volume control VR13 o 0 0 0 o 0 0 o 1 1 1 1 1 1 1 1 VR12 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VRII 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VR1O 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume gain (dB) -8. O -7. o -6. O -5.0 -4. o -3. o -2.0 -1.0 0 +1.0 +2. o +3. o +4. o +5. o +6. O +7. o
[AK2358FI
b) VR2, VR3 volume control VR22 VR21 VR23 VR32 VR31 VR33 o 0 0 0 0 0 101011 o 0 1 0 o 1 0 1 0 o 1 1 VR20 VR30 0 1 Volume gain (dB) -4. -3. -3. -2. -2. -1. -1. -0. o 5 o 5 o 5 0 5
101 #
1 0 1 0 1
101
11
1
1
11
I
I
1
0 0
0 1 1 1
1
0
1 1
1
0
0 1
1
0
+1.0 +1.5 +2. o +2.5 +3 n
1
11
1
I
1
10101 0 1 I
1 (-1
0152-E--OO
17
1996, 12
ASAH 1 KASEI c ) VR4 volume control
I
!
VR42
VR41
I
VR40
I
o
o o o 1 1 1 1
0
0 1 1 0 0
1
0
1 0 1 0 1
\
0
1
1
Volume ~ain (dB) -;2 -9 -6 -3 0 +3 +6 +9
I
Note) By reset, the gain of all volumes are set to OdB and RECSW bit is changed to "o". 4) MSK MODEM reception data
I I
I
D7 RD7 I D6 IDS I RD6 RD5
Data D4 \ D3 RD4 RD3
I ]D2 I D1 I RD2 RD 1 Function "1'': l.2kHz "O" :2. 4kHz DO
RDO
Data name RDO t RD7
MSK reception data RD7 is the first received data.
0152-E-00
- 18
1996 [2
ASAHI KASEI
I
[AK2358FI MSK Modem I
MSK signal transmission flow
MSK signal transmission
W
MSK transmission data are transmitted synchronized to TCLK.
N
: MSK transmission start
: During MSK transmission
Transmission of the
I
TDE= "1"
I
: MSK data transmission completion
WAIT for 2 ms or more
T
TXAFSW = "O"
: Switching to voice signal
A
(1) Set the serial register "TDE" to "O" and "TXAFSW" to "l", so that lISK transmission state is provided. (2) A 2400Hz clock is put mt from TCLK. Synchronizing with the rising edge of TCLK, AK2358F reads the MSK transmission data from TDATA pin and put out them 10 MOD pin. (3) After the transrniss!on of the necessary number of signal bit, "TDE" of the serial register is set to l". (4) Afterwards, before switching to a voice signal transmission mode, wait at east 2ms after "TDE" has set to "l" to complete the MSK signal final bit transmission. Then set TXAFSW register to "O".
0152-E-00 " 19
1996/12
ASAHI KASEI MSK Signal Reception
USK signal r e c e p t i o n
[AK2358FI
d=
FSL set to "O". N RXAFSW = "1" I
: S e t s o t h a t a frase d e t e c t i o n s i g n a l ( F D ) i s p u t o u t fros t h e RDF/FD p i n .
: Synchronization frame detection?
: Reception voice u u t e
7
FSL set to " 1" N Reception data read i ng
: S e t s o t h a t a n NSK s i g n a l r e c e p t i o n f l a g (RDF) i s p u t o u t from t h e RDF/FD p i n .
: Reception of 8 bit of data?
: R e a d i n g o f 8 b i t o f d a t a . c h a n g e t o RDF/FD = " H "
II
FCLN set to "O"
I
I
: Waiting for t h e n e x t s y n c h r o n i z a t i o n
frame
A
(1) If the internal register "FCLN" is "O", the internal nodes RDATA, RCLK are fixed to "l". (2) After a synchronization frame is detected, FD goes to "L" during the period "T", then FCLN is set to "l". (3) RDATA and RCLK put out the data following to the synchronized frame pattern, and these are stored in the internal buffer. (4) After 8 bit of reception data have been entered to the internal buffer, RDF goes "L". (5) After the CPU detect that RDF is "L", it puts out 8 clock bits to SCLK, then read 8 bit of reception data from the SDATA pin. (6) with input of 8 clock bits to SCLK, RDF goes "H". (7) Afterwards, by repeating the steps (4) and (5) the necessary data bits are read. (8) After the necessary data have been read, DIR goes "H", "FCLN" is set to "O" via the serial interface, the internal nodes RDATA and RCLK are set to "l", then the system waits for lhe next synchronization frame.
0152-E-00
-20"
1996/12
ASAHI KASEI
[AK2358FI Application Circuit Example I
I
s Application Circuit
OAMP 1 Use as a transmitting microphone amplifier. The gain should be less than 30dB. To eliminate high frequency noise component over than 100kHz from input signal, Ist order or 2nd order anti-aliasing filter is necessary. The following drawing is one example of the 2nd order anti-aliasing filter, which has 30dB gain and 10kHz cut-off frequency. /J \. A AMP1
<
TXINO
~3 C1=2200PF C2=33PF
f\ ) TXINR2 & cl
Rl=R2=10k Q R3-330k Q
LSI @3moothing filter for MOD output signal Realize low-pass filter to eliminate l12kHz clock signal component from MOD pin output signal. The following is one example of the 1st order low-pass filter which has 8.7kHz cut-off frequency. 10kQ of the modulator load resistor(RL) provide 3.3dB signal attenuation. R
MOD
C2 R=3.9k 52
cl=4700pF
-T
`ll =`L T
CZ=OI~F
RL=lOk Q (Load resistance of MOD)
0AMP2 The amplifier for the receiving gain adjustment and anti-aliasing filtering to eliminate high frequency noise component over 100kHz. The gain should be less than 30dB. The following is an example of the 2nd order low pass filter, which has 20 dB gain and 40kHz cut-off frequency. RXINO C1=560PF C2=27pF Rl=lOkQ AMP2
<
R2=9. lkQ R3=100k Q LSI
0152-E-00 - 21
1996, 12
ASAHI KASEI
[AK2358FI
0AMP3 The smoothing filter to eliminate 448kHz clock component from EXPOUT signal is provided by this amplifier. Also it works to adjust the receiving gain. Adding the other pass signal may be possible. The following is one example of the 1st order low-pass filter, which has OdB gain , 19kHz cut-off frequency. EXPOUT C2 RI RXAFIN c1 @ RXAF ++ AMP3 LSI R2 Cl=150pF C2=0 .022 pF Rl=R2=56k Q
OAGNIl stabilizing capacitor To stabilize the AGND potential, connect capacitors larger than 0.3KF between TACND pin, RAGND pin and AVSS pin. Also between AGNDIN pin and AVSS pin some capacitor is necessary to reduce the ripple of the power.
C-1 /iF
LSI
QVDD stabilizing capacitor To reduce the noise on VDD, connect capacitors between VDD and VSS. VDD VDD cl
+
C1-22,UF
C2
(Aluminium Electrolytic Capacitor) C2-O.l~F (Ceramic Capacitor)
Vss b
<
LSI
0152-E-00 22
1996 12
ASAHI KASEI
[AK2358FI
OCrystal oscillator - Crystal resonator , resistor and capacitors should be connected as shown Fig.3 for on-chip oscillator operation. - For external clock operation, if the high(H) level of the input clock signal amplitude equals to or is greater than 1.5V, and the low(L) level equals to or is smaller than 0.5V, then connection should be made as shown in Fig.4. If the input clock signal amplitude (peak-to-peak) equals to or is smaller than lV, and equals to or is greater than 200mV, then AC coupling should be as illustrated in Fig.5.
1=
XIN
22pF
XOUT
3.58MHz
lM i 22pF * -
FXIN Fig.4
External clock signal
Fig.3
IT r
XIN XOUT
O.Ol#F ~External clock signal
lM Cl
fig.5
OLimit level adjusting resistor The limiting level can be controled externally by applying DC voltage to LIMIV pin. Applied DC voltage should be larger than TAGND, then the limiting level is shown as TAGND*Va(V), while Va is the voltage between LIMIV and TAGND. Keeping LIMIV pin open provides default limit level. See following exampleVDD LIMLV R .+: LSI R=50k .$2
Vss
0152-E-00
1996/]2 -23-
ASAHI KASEI
[AK2358FI Package
I
s Marking
I
[Contents of XXXYZ] XXX: Date of manufacture Last digit of the year, week number of the year as 2 digits Y: Production lot number Z: Assembled place
s Shape and dimensions of the package
24 pin VSOP
Unit: mm 7.8%;
2
IUIUURUUURU[
3
o
0.2
Note:
+q ._ `K
*
--i !=
0.65
Q@@4L
CUN
0
T-F-
Dimensions marked by * do not include residual resin.
& 0-10"
A
D e t a i l of p a r t Ma
eriall Resin: Low-stress Lead frame: Cu
t y p e epoxy resin
0152-E-00
24
1996;12
-,
IMPORTANT NOTICE . These products andtheir specifications aresubject tochange without notice. Before considering anyuseorapPfiCatiOn, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. . AKM assumes noliabili~ forinfringernent ofanypatent, intellectual property, orotherright in the application or use of any information contained herein. . Any export of these products, or devices or systems containing them, May require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials. . AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device Or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life SUppOfl or r-maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in IOSS of fife or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or pedorm may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of pefiormance and reliability. q It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise plaCeS the product with a third party to notify that pa~ in advance of the above content and conditions, and the buyer or distributor agr@eS tO aSSUMe ally and all responsibility and liability for and hold AKM harmless from any and all C]aiMS afiSing frOn'1 the use of said product in the absence of such notification.

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